LTC3605A [Linear Systems]
20V, 2.5A Synchronous Monolithic Step-Down Regulator; 20V ， 2.5A单片同步降压型稳压器
| 型号： | LTC3605A |
| 厂家： | 
Linear Systems |
| 描述： | 20V, 2.5A Synchronous Monolithic Step-Down Regulator |
| 文件： | 总28页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3626
20V, 2.5A Synchronous
Monolithic Step-Down Regulator with
Current and Temperature Monitoring
FEATURES
DESCRIPTION
TheLTC®3626isahighefficiency,monolithicsynchronous
n
3.6V to 20V Input Voltage Range
Wide Output Voltage Range of 0.6V to 97% V
Optimized for 0.6V to 6V
n
buck regulator using a phase-lockable controlled on-time,
current mode architecture capable of supplying up to 2.5A
of output current. The operating supply voltage range is
3.6V to 20V, making it suitable for a wide range of power
supply applications.
IN
n
Low R
Integrated Switches Provide Up to 95%
DS(ON)
Efficiency
n
n
n
n
n
n
n
Up to 2.5A of Output Current
Average Input and Output Current Monitoring
Theoperatingfrequencyisprogrammablefrom500kHzto
3MHz with an external resistor allowing the use of small
surface mount inductors. For applications sensitive to
switching noise, the LTC3626 can be externally synchro-
nized over the same frequency range. An internal phase-
lockedloopalignstheon-timeofthetoppowerMOSFETto
theinternalorexternalclock.Thisuniquecontrolledon-time
architecture is ideal for high step-down ratio applications
that demand high switching frequencies and fast transient
response. An internal phase lock loop servos the on-time
of the internal one-shot timer to match the frequency of
the internal clock or an applied external clock.
Programmable Average Input/Output Current Limit
Die Temperature Monitor and Programmable Limit
Adjustable Switching Frequency: 500kHz to 3MHz
External Frequency Synchronization
Current Mode Operation for Excellent Line and Load
Transient Response
n
n
0.6V Reference with 1% Accuracy Over Temperature
User Selectable Burst Mode® or Forced Continuous
Operation
n
n
n
n
Short-Circuit Protected
Output Voltage Tracking Capability
Power Good Status Output
The LTC3626 offers two operational modes: Burst
Mode and forced continuous mode to allow the user
to optimize output voltage ripple, noise and light load
efficiency for a given application.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258,
6304066, 6476589, 6774611, 5994885.
Available in Small, Thermally Enhanced, 20-Lead
(3mm × 4mm) QFN Package
APPLICATIONS
n
Distributed Power Systems
n
Battery-Powered Instruments
n
Point-of-Load Power Supply
Efficiency vs Load Current
TYPICAL APPLICATION
100
V
= 3.3V
OUT
V
90
80
70
60
50
40
30
20
10
0
IN
PV
SV
IN
IN
3.6V TO 20V
10
47µF
RUN
BOOST
LTC3626
0.1µF
2.2µH
PGOOD
1
V
3.3V
2.5A
INTV
TRACK/SS
ITH
OUT
CC
SW
2.2µF
47µF
115k
0.1
0.01
0.001
MODE/SYNC
TSET
V
ON
22pF
IMON
FB
RT
IN
Burst Mode
OPERATION
TMON
25.5k
IMON
OUT
V
V
= 12V
= 5V
IN
IN
324k
SGND
PGND
1µF
5.1k
3626 TA01
1
10
100
1000
10000
3626 TA01b
LOAD CURRENT (mA)
3626f
1
LTC3626
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
PV ........................................................... –0.3V to 22V
IN
SV ........................................................... –0.3V to 22V
IN
BOOST .................................................... –0.3V to 25.6V
BOOST-SW................................................ –0.3V to 3.6V
20 19 18 17
INTV ...................................................... –0.3V to 3.6V
BOOST
1
2
3
4
5
6
16
15
14
13
12
11
PV
PV
SV
CC
IN
IN
IN
INTV
CC
ITH, RT, FB.................................–0.3V to INTV + 0.3V
CC
V
ON
21
PGND
MODE/SYNC ..............................–0.3V to INTV + 0.3V
CC
TSET
TMON
SGND
RUN
RT
TRACK/SS, IMON , IMON
...–0.3V to INTV + 0.3V
IN
OUT
CC
TSET, TMON ..............................–0.3V to INTV + 0.3V
CC
ITH
SW, RUN.......................................... –0.3V to V + 0.3V
IN
7
8
9 10
PGOOD....................................................... –0.3V to 22V
V
ON
............................................................ –0.3V to 18V
SW Source Current (DC, Note 2)..............................2.5A
Operating Junction Temperature Range
(Notes 3, 4) ........................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
= 125°C, θ = 47°C/W
T
JMAX
JA
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3626EUDC#PBF
LTC3626IUDC#PBF
TAPE AND REEL
PART MARKING*
LGCC
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3626EUDC#TRPBF
LTC3626IUDC#TRPBF
–40°C to 125°C
–40°C to 125°C
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
LGCC
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3626f
2
LTC3626
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). PVIN = SVIN = 12V unless otherwise specified.
SYMBOL
PV
PARAMETER
CONDITIONS
MIN
3.0
3.6
0.6
TYP
MAX
20
20
6
UNITS
l
l
Input Supply Range
Input Supply Range
Output Voltage Range (Note 5)
V
V
V
IN
SV
IN
V
V
= V
ON OUT
VOUT
I
Input DC Supply Current
Q
Forced Continuous Operation
MODE = 0, R = 158k, I , I , TMON,
RT
CC
IN OUT
PV
TSET = INTV
30
900
39
1200
µA
µA
IN
SV
IN
Sleep Current
PV
V
> 0.6V, I , I , TMON, TSET,
FB IN OUT
MODE = INTV
30
270
39
350
µA
µA
IN
CC
SV
IN
Shutdown
PV
I
= 0A, V
= 0V
LOAD
RUN
0.01
13
2
17
µA
µA
IN
SV
IN
l
V
Feedback Reference Voltage
0.594
0.600
0.01
0.1
0.606
V
%/V
%
FB
V
V
Line Regulation
Load Regulation
V
= 3.6V to 20V
VIN
∆V
∆V
FB
FB
LINE(REG)
LOAD(REG)
ITH = 0.6V to 1.5V
= 0.6V
Feedback Pin Input Current
Error Amplifier Transconductance
Minimum On-Time
V
30
nA
mS
ns
FB
ITH = 1.2V
=1V, V = 3.6V
1.5
20
t
t
V
VON
ON(MIN)
VIN
Minimum Off-Time
PV = SV = 6V
40
60
ns
OFF(MIN)
IN
IN
Valley Switch Current Limit
Oscillator Frequency
2.4
2.9
3.6
A
f
V
= INTV
1.4
1.7
2.5
2
2
3
2.6
2.3
3.5
MHz
MHz
MHz
OSC
RT
CC
= 158k
= 105k
R
R
RT
RT
R
Top Switch On-Resistance
Bottom Switch On-Resistance
115
70
mΩ
mΩ
DS(ON)
IMON
Current (Note 6)
I
SW
I
SW
I
SW
= 2.5A
= 1.5A
= 0.5A
148.5
89.1
29.7
156.25
93.75
31.25
164.0
98.4
33.5
µA
µA
µA
OUT
l
l
I
Limit Regulation Voltage
1.15
1.22
1.28
V
OUT
IMON Current (Note 6)
I
I
I
= 2.5A, 20% Duty Cycle
= 1.5A, 20% Duty Cycle
= 0.5A, 20% Duty Cycle
29.7
17.8
5.9
31.25
18.75
6.25
32.8
19.7
6.7
µA
µA
µA
IN
SW
SW
SW
I
Limit Regulation Voltage
1.15
1.22
1.5
200
50
1.28
V
V
IN
Internal Temperature Monitor
T = 25°C
A
Internal Temperature Monitor Slope (Note 7)
Temperature Limit Hysteresis
°C/V
mV
PV Overvoltage Lockout Threshold
IN
PV Rising
IN
21.5
20.5
V
V
IN
PV Falling
20
V
V
INTV Voltage
3.6V < V < 20V
3.1
3.3
0.6
3.5
V
INTVCC
CC
IN
INTV Load Regulation (Note 8)
I
= 0mA to 20mA
%
CC
INTVCC
l
l
RUN Threshold
RUN Rising
RUN Falling
1.19
0.97
1.23
1.0
1.27
1.03
V
V
RUN
RUN Leakage Current
V
= 20V
0
1
μA
VIN
PGOOD Good-to-Bad Threshold
FB Rising
FB Falling
8
–8
10
–10
%
%
3626f
3
LTC3626
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). PVIN = SVIN = 12V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGOOD Bad-to-Good Threshold
FB Rising
FB Falling
–3
3
–5
5
%
%
Power Good Filter Time
PGOOD Pull-Down Resistance
Switch Leakage Current
Internal Soft-Start Time
TRACK/SS Pull-Up Current
MODE Threshold Voltage
20
40
20
μs
Ω
R
10mA Load
PGOOD
V
V
= 0V
0.01
400
1.4
1
μA
μs
μA
RUN
t
I
from 10% to 90% Full Scale
FB
700
SS
TRACK/SS
l
l
MODE V
MODE V
1.0
1.4
V
V
IH
IL
0.4
l
SYNC Threshold Voltage
MODE Input Current
SYNC V
V
IH
MODE = 0V
MODE = INTV
–1.5
1.5
μA
µA
CC
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: Output voltages above 6V are not optimized for controlled
on-time operation. Refer to the Applications Information section for
further discussions related to the output voltage range. Verified at test by
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by long term current density limitations.
Note 3: The LTC3626 is tested under pulsed load conditions such that
T ≈ T . The LTC3626E is guaranteed to meet performance specifications
J
A
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization, and
correlation with statistical process controls. The LTC3626I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance, and other environmental
factors.
comparison of measured on-time to V voltage.
ON
Note 6: Tested in a proprietary test mode, where I flows through the
SW
synchronous switch only.
Note 7: Guaranteed by design.
Note 8: Maximum allowed current draw when used as a regulated output
is 5mA. This supply is only intended to supply additional DC load currents
as needed and not intended to regulate large transient or AC behavior as
these waveforms may impact LTC3626 operation.
3626f
4
LTC3626
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted.
Efficiency vs Load Current
(Burst Mode Operation)
Efficiency vs Load Current (Forced
Continuous Mode Operation)
Efficiency vs Load Current
(Burst and Forced Continuous)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V
V
= 1.8V
OUT
Burst Mode OPERATION
OUT
FORCED
CONTINUOUS
MODE OPERATION
V
V
V
V
= 4V
V
V
V
V
= 4V
IN
IN
IN
IN
IN
IN
IN
IN
= 8V
= 8V
V
V
= 5V
= 3.3V
= 12V
= 20V
= 12V
= 20V
OUT
OUT
1
10
100
1000
10000
1
10
100
1000
10000
1
10
100
1000
10000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3626 G01
3626 G02
3626 G02
Efficiency vs Input Voltage
(Burst Mode Operation)
Efficiency vs Frequency (Forced
Continuous Mode Operation)
Reference Voltage
vs Temperature
100
90
80
70
60
50
40
30
20
10
0
0.606
0.604
0.602
0.600
100
95
90
85
80
75
70
65
60
V
= 3.3V
OUT
V
= 1.8V
OUT
0.598
0.596
0.594
f = 500kHz
f = 1MHz
f = 2MHz
f = 3MHz
I
I
I
I
= 1A
LOAD
LOAD
LOAD
LOAD
= 2.5A
= 100mA
= 10mA
1
10
100
1000
10000
–50
25
50
75
100 125
12 14
–25
0
4
6
8
10
16 18 20 22
LOAD CURRENT (mA)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3626 G05
3626 G06
3626 G04
Internal MOSFET RDS(ON)
vs Temperature
Temperature Monitor
vs Temperature
125
2.0
1.9
160
140
120
100
TOP SWITCH
75
50
25
0
1.7
1.6
1.5
1.4
1.2
100
80
60
40
20
BOTTOM SWITCH
–25
–50
1.1
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
3626 G08
3626 G07
3626f
5
LTC3626
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted.
Output Current Monitor
vs Output Current
Output Current Monitor Error
vs Output Current
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
156
125
94
5
4
3
2
1
0
–1
–2
–3
–4
–5
63
T
T
T
= 85°C
= 25°C
= –40°C
A
A
A
T
T
T
= 85°C
= 25°C
= –40°C
A
A
A
31
1.5 1.75
0.5 0.75 1.0 1.25
2.0 2.25 2.5
1
1.25
1.75
2
2.25
2.5
1.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3626 G09
3626 G10
Input Current Monitor
vs Input Current
Input Current Monitor Error
vs Input Current
Quiescent Current vs VIN
(Burst Mode Operation)
10
8
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
31
28
25
22
19
16
13
500
450
400
350
300
250
200
150
100
6
4
2
0
–2
–4
–6
–8
–10
T
T
T
= 85°C
= 25°C
= –40°C
T
T
T
= 85°C
= 25°C
= –40°C
A
A
A
T
T
T
= 85°C
= 25°C
= –40°C
A
A
A
A
A
A
9
6
0.3 0.35
4
6
12 14
INPUT VOLTAGE (V)
20
0.1 0.15 0.2 0.25
0.4 0.45 0.5
8
10
16 18
0.16
0.20 0.24 0.28
0.32
0.36 0.48
0.40 0.44
INPUT CURRENT (A)
INPUT CURRENT (A)
3626 G11
3626 G13
3626 G12
Oscillator Frequency
vs Temperature
Oscillator Internal Set Frequency
vs Temperature
TRACK/SS Pull-Up Current
vs Temperature
2.6
2.4
2.2
2.0
10
8
2.0
1.8
R
= 158kΩ
R
= INTV
CC
T
T
6
1.6
1.4
1.2
1.0
0.8
4
2
0
–2
–4
–6
–8
–10
1.8
1.6
1.4
0.6
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50
0
25
50
75 100 125
–50
25
50
75
100 125
–25
–25
0
TEMPERATURE (°C)
TEMPERATURE (°C)
3626 G15
3626 G14
3626 G16
3626f
6
LTC3626
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted.
Output Voltage vs Time
(Burst Mode Operation)
Output Voltage vs Time (Forced
Continuous Mode Operation)
Load Regulation
1.0
0.8
V
V
SW
5V/DIV
SW
0.6
5V/DIV
0.4
0.2
V
OUT
V
OUT
20mV/DIV
20mV/DIV
0
–0.2
–0.4
–0.6
–0.8
–1.0
I
L
I
L
1A/DIV
1A/DIV
3626 G18
3626 G19
V
LOAD
= 1.8V
= 100mA
4µs/DIV
V
LOAD
= 1.8V
= 100mA
2µs/DIV
OUT
OUT
Burst Mode OPERATION
FORCED CONTINUOUS
I
I
0
0.5
1
I
1.5
(A)
2
2.5
LOAD
3626 G17
Start-Up from Shutdown
(Burst Mode Operation)
Start-Up from Shutdown (Forced
Continuous Mode Operation)
Output Tracking
V
OUT
RUN
2V/DIV
RUN
2V/DIV
1V/DIV
V
V
OUT
1V/DIV
OUT
1V/DIV
TRACK/SS
I
I
L
1A/DIV
L
V
FB
1A/DIV
500mV/DIV
3626 G20
3626 G21
3626 G22
V
LOAD
= 1.8V
= 200mA
2ms/DIV
V
= 1.8V
200µs/DIV
V
= 1.8V
200µs/DIV
OUT
OUT
OUT
I
I
= 200mA
I
= 200mA
LOAD
C
LOAD
C
= 2.2nF
= 2.2nF
SS
SS
Load Step
(Burst Mode Operation)
Load Step (Forced Continuous
Mode Operation)
I
TH
= INTV
I
TH
= INTV
CC
CC
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
I
I
L
L
2.5A/DIV
2.5A/DIV
3626 G23
3626 G24
V
C
= 1.8V
= 47µF
= 100mA TO 2.5A
20µs/DIV
V
C
= 1.8V
= 47µF
= 100mA TO 2.5A
20µs/DIV
OUT
OUT
OUT
OUT
I
I
LOAD
LOAD
3626f
7
LTC3626
PIN FUNCTIONS
BOOST (Pin 1): Boosted Floating Driver Supply Pin. The
(+) terminal of the external bootstrap capacitor connects
to this pin while the (–) terminal connects to the SW pin.
The normal operation voltage swing of this pin ranges
IMON (Pin 7): Average Input Current Monitor. A current
IN
proportional to the average input current flows out of this
pin.PullthispintoINTV todefeattheinputcurrentmoni-
CC
tor function. An error amplifier compares the voltage on
this pin to 1.2V (typical) and throttles the average current
as required based on the external resistor value from this
pin to SGND. Selecting the external resistor value allows
the user to control the maximum average input current.
See the Applications Information section for more details.
from INTV to PV + INTV .
CC
IN
CC
INTV (Pin 2): Internal 3.3V Regulator Output Pin. This
CC
pin should be decoupled to PGND with a low ESR ceramic
capacitor of value 1µF or greater. The 3.3V regulator is
disabled when the RUN pin is low.
IMON
(Pin 8): Average Output Current Monitor Pin. A
OUT
V
(Pin 3): On-Time Voltage Input. This pin sets the
ON
current proportional to the average output current flows
voltage trip point for the on-time comparator. Tying this
out of this pin. Pull this pin to INTV to defeat the output
CC
pin to the output voltage makes the on-time proportional
to V
current monitor function. An error amplifier compares
the voltage on this pin to 1.2V (typical) and throttles the
average current as required based on the external resis-
tor value from this pin to SGND. Selecting the external
resistor value allows the user to control the maximum
average output current. See the Applications Information
section for more details.
when V
< 6V. When V
> 6V, the switching
OUT
OUT
OUT
frequency may become higher than the set frequency. The
impedance of this pin is nominally 160kΩ.
TSET (Pin 4): Temperature Limit Set Pin. The voltage at
this pin determines the threshold for internal temperature
shutdown. When the voltage at TMON reaches the volt-
age at TSET, the LTC3626 will trigger an overtemperature
fault. An overtemperature fault will initiate part shutdown,
reset soft-start and an attempt to restart once the internal
temperaturefalls10°C(typical)fromthethresholdgivenat
TSET. The voltage at TSET has no impact on a secondary
overtemperature shutdown threshold within the LTC3626
as described in Note 4 of the Electrical Characteristics
section.
TRACK/SS(Pin 9):Output Voltage Tracking andSoft-Start
Input.Forcingavoltagebelow0.6Vonthispinoverridesthe
internalreferenceinputtotheerroramplifier.TheLTC3626
will servo the FB pin to the TRACK/SS voltage under this
condition. Above 0.6V, the tracking function stops and the
internalreferenceresumescontroloftheerroramplifier.An
internal1.4µA(typical)pull-upcurrentfromINTV allows
CC
a soft-start function to be implemented by connecting an
external capacitor between this pin and ground. See the
Applications Information section for more details.
TMON (Pin 5): Temperature Monitor Output. A voltage
proportional to the measured on-die temperature will ap-
pear at this pin. The voltage-to-temperature scaling factor
is 200°K/V. See the Applications Information section for
detailed information on the TMON function. Tie this pin to
FB(Pin10):OutputVoltageFeedback. Thispinistheinput
to the error amplifier that compares the feedback voltage
to the internal 0.6V reference voltage. Connect this pin to
the appropriate resistor divider network to program the
desired output voltage.
INTV to disable the temperature monitor circuit.
CC
SGND (Pin 6): Signal Ground Pin. This pin should have a
low noise connection to reference ground. The feedback
resistor network, external compensation network, current
monitorcomponents,andR resistorshouldbeconnected
to this ground.
T
3626f
8
LTC3626
PIN FUNCTIONS
ITH(Pin11):ErrorAmplifierOutputandSwitchingRegula-
tor Compensation Point. Connect this pin to appropriate
external components to compensate the regulator loop
frequency response. Connect this pin to INTV to use
the default internal compensation.
PGOOD (Pin 18): Open-Drain Power Good Output Pin.
PGOOD is pulled to ground when the voltage at the FB pin
is not within 8% (typical) of the internal 0.6V reference.
PGOOD becomes high impedance once the voltage at
the FB pin returns to within 5% (typical) of the internal
reference.
CC
RT (Pin 12): Oscillator Frequency Program Pin. Connect
an external resistor, between 640k to 105k, from this pin
to SGND to program the LTC3626 switching frequency
from 500kHz to 3MHz. When RT is tied to INTV , the
switching frequency will default to 2MHz (typical).
SW (Pins 19, 20): Switch Node Connection to Inductor.
Connect this pin to the SW side of the external inductor.
The normal operation voltage swing of this pin ranges
CC
from ground to PV .
IN
RUN (Pin 13): Regulator Enable Pin. Enables chip opera-
tion by applying a voltage above 1.25V. A voltage below
1.0V on this pin places the part into shutdown. Do not
float this pin.
PGND (Exposed Pad Pin 21): Power Ground Pin. The (–)
terminal of the input bypass capacitor, C , and the (–) of
IN
the output capacitor, C , should be tied to this pin with
OUT
a low impedance connection. This pin must be soldered
to the PCB to provide low impedance electrical contact to
ground and good thermal contact to the PCB.
SV (Pin 14): Signal Power Supply Input. This pin sup-
IN
plies current to the internal 3.3V regulator.
PV (Pins 15, 16): Main Power Supply Input. These pins
IN
should be closely decoupled to PGND with a low ESR
capacitor of value 10µF or more.
MODE/SYNC (Pin 17): Mode Selection and External
Synchronization Input. This pin places the LTC3626 into
forced continuous operation when tied to ground. High
efficiency Burst Mode operation is enabled by either
floating this pin or tying this pin to INTV . When driven
CC
with an external clock, an internal phase-locked loop
will synchronize the phase and frequency of the internal
oscillator to that of incoming clock signal. During external
clock synchronization, the LTC3626 will default to forced
continuous operation.
3626f
9
LTC3626
FUNCTIONAL DIAGRAM
R
IN
C
IN2
C
IN
V
ON
RUN
SV
IN
PV
IN
1.25V
160k
+
RUN
–
3.3V
REG
A
V
= 1
PV
I
IN
0.72V
6V
RUN
INTV
CC
I
ON
RT
C
C
V
VON
INTVCC
ON
t
=
R
S
OSC
ON
CONTROLLER
I
ON
ION
R
RT
BOOST
SW
Q
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
TG
BG
BST
L
M1
MODE/SYNC
OSC
PLL-SYNC
C
OUT
M2
I
I
REV
CMP
PGND
–
–
+
+
–
SENSE
COMP
SELECT
+
SENSE
ITH
R
COMP
R1
R2
FB
C
COMP
IDEAL
DIODES
0.6V
REF
+
–
EA
–
–
+
+
INTERNAL
SOFT-START
1.2V
IMON
IMON
OUT
OUTPUT
CURRENT
MONITOR
INTV
CC
IN
1.4µA
C
SS
TRACK/SS
0.648V
–
DUTY
CYCLE
OV
UV
SGND
PGOOD
+
TRACK
–
+
–
BURST FC
SS
MODE
SELECT
0.552V
+
MODE/SYNC
0.48V AT START-UP
0.10V AFTER START-UP
+
T
1V/200k
+
J
TEMP
FAULT
CONTROL
–
–
TMON
TSET
3626 BD
3626f
10
LTC3626
OPERATION
The LTC3626 is a current mode, monolithic, step-down
regulatorcapableofprovidingupto2.5Aofoutputcurrent
from an input supply as high as 20V. Its unique controlled
on-timearchitectureallowsextremelylowstep-downratios
whilemaintainingaconstantswitchingfrequency.Thepart
is enabled by raising the RUN pin above 1.25V (typical).
tyingtheMODE/SYNCpintoground, placingtheLTC3626
into forced continuous mode. In forced continuous mode,
continuous synchronous operation occurs regardless of
the output load current.
TheoperatingfrequencyisdeterminedbythevalueoftheR
T
resistor, which programs the current forthe internaloscil-
lator. An internal phase-locked loop adjusts the switching
regulator on-time to track the internal oscillator edge and
Main Control Loop
In normal operation the internal top power MOSFET is
turned on for a fixed interval determined by an internal
one-shot timer (“ON” signal in the Functional Diagram).
When the top power MOSFET turns off, the bottom power
force a constant switching frequency, subject to t and
ON
t
time constraints as shown in the Electrical Character-
OFF
istics table. Alternatively, the RT pin can be connected to
the INTV pin which causes the internal oscillator to run
CC
MOSFETturnsonuntilthecurrentcomparator,I
,trips,
at the default frequency of 2MHz. Finally, a clock signal
can be applied to the MODE/SYNC pin to synchronize the
switching frequency to an external source. The regulator
defaults to forced continuous operation when an external
clock signal is applied.
CMP
thus restarting the one-shot timer and initiating the next
cycle. The inductor current is monitored by sensing the
voltage drop across the bottom power MOSFET. The volt-
age at the ITH node sets the I
comparator threshold
CMP
corresponding to the inductor valley current. The error
amplifier, EA, adjusts the ITH voltage by comparing an
Output/Input Current Monitor and Limit
internal0.6Vreferencevoltagetothefeedbacksignal, V ,
FB
The LTC3626 provides a scaled replica of the average
output current and a scaled replica of the average input
derived from the output voltage. If, for example, the load
currentincreases, theoutputvoltagewilldecreaserelative
to the 0.6V reference. The ITH voltage then rises until the
average inductor current matches that of the load current.
current at the IMON
and IMON pins respectively. The
OUT
IN
average current at each of these pins will be 1/16,000th
of the measured average current. Further, the voltage at
each pin is continuously fed to independent current limit
amplifiers that have a voltage reference at 1.2V. Thus, a
programmableaveragecurrentlimitfortheoutputcurrent
and/or input current may be obtained by placing a resistor
of suitable value at the pin of interest so as to produce
1.2V at the desired current limit. When the current limit
feature is used, a compensation capacitor (1µF typical)
should be placed in parallel with the chosen resistor. The
output or input current monitor and limit circuits may be
At light load currents the inductor current can drop to
zero or become negative. If the LTC3626 is configured for
Burst Mode operation, this inductor current condition is
detected by the current reversal comparator, I , which
REV
in turn shuts off the bottom power MOSFET and places
the part into a low quiescent current sleep state resulting
in discontinuous operation and increased efficiency at low
load currents. Both power MOSFETs remain off with the
part in sleep and the output capacitor supplying the load
current until the ITH voltage rises sufficiently to initiate
another cycle. Discontinuous operation is disabled by
individually disabled by pulling IMON
or IMON to
OUT
IN
INTV as appropriate.
CC
3626f
11
LTC3626
OPERATION
Temperature Monitor and Limit
voltage at the TSET pin has no impact on the secondary
overtemperature shutdown threshold within the LTC3626
as described in Note 4 of the Electrical Characteristics.
The LTC3626 produces a voltage at the TMON pin pro-
portional to the measured on-die temperature. The on-die
temperature-to-voltagescalingfactoris200°K/V.Thus,to
obtain the on-die temperature in degrees Kelvin, simply
multiplythevoltageprovidedattheTMONpinbythescaling
factor.To obtaintheon-dietemperatureindegreesCelsius,
subtract 273 from the value obtained in degrees Kelvin.
“Power Good” Status Output
The PGOOD open-drain output will be pulled low if the
regulatoroutputexitsa 8%windowaroundtheregulation
point. This condition is released once regulation within a
5% window is achieved. To prevent unwanted PGOOD
The voltage produced at TMON is continuously fed to a
limit comparator that has the voltage at the TSET pin as its
referenceinput.Whentriggered,thiscomparatorgenerates
anovertemperaturefaultthatwillinitiatepartshutdownand
resetofsoft-start. Thus, amaximumjunctiontemperature
limit may be set by providing a voltage at the TSET pin
that corresponds to the temperature limit of interest. The
voltage at the TSET pin may be derived from a resistor
glitches during transients or dynamic V
changes, the
OUT
LTC3626 PGOOD falling edge includes a filter time of
approximately 40μs.
PV Overvoltage Protection
IN
To protecttheinternalpowerMOSFETdevicesagainsttran-
sient voltage spikes, the LTC3626 continuously monitors
the PV pin for an overvoltage condition. When PV rises
IN
IN
divider from INTV , subject to the current constraints
CC
above 21.5V (typical), the regulator suspends operation
listed in the Electrical Characteristics section, or may be
driven externally. The LTC3626 will clear the overtem-
perature fault and restart once the internal temperature
falls 10°C (typical) from the threshold given at TSET. The
by shutting off both power MOSFETs and resets soft-start.
Once PV drops below 20.5V (typical), the regulator re-
IN
starts normal operation by executing a soft-start.
3626f
12
LTC3626
APPLICATIONS INFORMATION
3500
3000
A generalLTC3626application circuitisshown on the first
page of this data sheet. External component selection is
largely driven by the load requirement and begins with the
selection of the inductor L. Once the inductor is chosen,
the input capacitor, C , the output capacitor, C , the
2500
2000
1500
1000
500
IN
OUT
internalregulatorcapacitor,C
tor, C , can be selected. Next, the feedback resistors
,andtheboostcapaci-
INTVCC
BST
are selected to set the desired output voltage. Finally, the
remaining optional external components can be selected
forfunctionssuchasexternalloopcompensation,PGOOD,
average output current monitor and limit, average input
current monitor and limit, and on-die temperature moni-
tor and limit.
0
400
600 700
0
100 200 300
500
R
T
(kΩ)
3626 F01
Figure 1. Switching Frequency vs RT
Operating Frequency
thiscondition,itispossibletheoperatingfrequencymaybe
higher than the programmed value. As a result, for output
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
voltages greater than 6V, the value of the R resistor may
T
needadjustmenttoobtainthedesiredoperatingfrequency.
Inductor Selection
Foragiveninputandoutputvoltage,theinductorvalueand
operatingfrequencydeterminetheinductorripplecurrent.
More specifically, the inductor ripple current decreases
with higher inductor value or higher operating frequency
according to the following equation:
The operating frequency, f, of the LTC3626 is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
V
f •L
VOUT
OUT
∆IL =
1–
V
IN
3.2E11
where ΔI = inductor ripple current, V = PV , f = operat-
L
IN
IN
RRT =
ing frequency and L = inductor value. A trade-off between
component size, efficiency and operating frequency can
be seen from this equation. Accepting larger values of
f
where R is in Ω and f is in Hz.
RT
ΔI allows the use of lower value inductors but results
L
Connecting the RT pin to INTV will assert the internal
CC
in greater core loss in the inductor, greater ESR loss in
the output capacitor, and larger output ripple. Generally,
highest efficiency operation is obtained at low operating
frequency with small ripple current.
default frequency f = 2MHz; however, this switching fre-
quency will be more sensitive to process and temperature
variations than using a resistor on RT (see Typical Perfor-
mance Characteristics).
A reasonable starting point for setting the ripple current is
The LTC3626 is not optimized for constant on-time opera-
tion when configured to generate output voltages greater
than6V.Thoughoutputregulationwillbemaintainedunder
approximately 1A . Note that the largest ripple current
P-P
occurs at the highest V . To guarantee the ripple current
IN
3626f
13
LTC3626
APPLICATIONS INFORMATION
does not exceed a specified maximum the inductance
should be chosen according to:
Table 1. Inductor Selection Table
INDUCTANCE DCR
MAX CURRENT
DIMENSIONS
HEIGHT
Vishay IHLP-2525CZ-01 Series
VOUT
f • ∆I
VOUT
0.33µH
20A
17.5A
15.5A
13A
11A
9A
3mm
L =
1–
3.5mW
6.5mm × 7mm
V
L(MAX)
IN(MAX)
0.47µH
0.68µH
0.82µH
1.0µH
1.5µH
2.2µH
3.3µH
4.7µH
6.8µH
4.0mW
5.0mW
6.7mW
9.0mW
14mΩ
18mΩ
28mΩ
37mΩ
54mΩ
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value but is very dependent on the
inductanceselected.Astheinductanceincreases,coreloss
decreases. Unfortunately, increased inductance requires
more turns of wire leading to increased copper loss.
8A
6A
5.5A
4.5A
Ferritedesignsexhibitverylowcorelossandarepreferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core materials saturate “hard,” meaning the inductance
collapses abruptly when the peak design current is ex-
ceeded. This collapse will result in an abrupt increase in
inductor ripple current, so it is important to ensure the
core will not saturate.
Toko FDV0620 Series
0.47µH
1µH
9A
2.0mm
3.0mm
8.3mW
7mm × 7.7mm
5.7A
18.3mW
NEC/Tokin MLC0730L Series
0.47µH
0.75µH
1µH
16.6A
12.2A
10.6A
4.5mW
7.5mW
9mW
6.9mm × 7.7mm
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroidal or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price versus size
requirements and any radiated field/EMI requirements.
New designs for surface mount inductors are available
from Toko, Vishay, NEC/Tokin, Cooper, Coilcraft, TDK and
Würth Electronik. Table 1 gives a sampling of available
surface mount inductors.
Cooper HCP0703 Series
0.47µH
0.68µH
0.82µH
1µH
17A
15A
13A
11A
9A
3.0mm
4.2mW
5.5mW
8mW
7mm × 7.3mm
10mW
14mW
1.5µH
TDK RLF7030 Series
1µH
6.4A
6.1A
5.4A
3.2mm
3.8mm
8.8mW
9.6mW
12mW
6.9mm × 7.3mm
7mm × 7.7mm
1.5µH
2.2µH
Würth Electronik WE-HC 744312 Series
0.47µH
0.72µH
1µH
16A
12A
11A
9A
3.4mW
7.5mW
9.5mW
10.5mW
C and C
Selection
IN
OUT
The input capacitance, C , is needed to filter the trapezoi-
IN
dal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
is recommended. The maximum RMS current is given by:
1.5µH
This formula has a maximum at V = 2V , where
IN
OUT
I
≅ I /2. This simple worst-case condition is com-
RMS
OUT
monlyusedfordesignbecauseevensignificantdeviations
V
V – V
OUT
(
)
OUT IN
do not offer much relief. Note that ripple current ratings
I
= I
OUT(MAX)
RMS
V
IN
3626f
14
LTC3626
APPLICATIONS INFORMATION
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further de-
rate the capacitor, or choose a capacitor rated at a higher
temperature than required.
Thus, a good place to start is with the output capacitor
size of approximately:
3• ∆IOUT
COUT
≈
f • VDROOP
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
Even though the LTC3626 design includes an overvoltage
protection circuit, care must always be taken to ensure
inputvoltagetransientsdonotposeanovervoltagehazard
to the part.
Thoughthisequationprovidesagoodapproximation,more
capacitance may be required depending on the duty cycle
and load step requirements. The actual V
should be
DROOP
verified by applying a load step to the output.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
available in small case sizes. Their high voltage rating
and low ESR make them ideal for switching regulator ap-
plications. However, due to the self-resonant and high-Q
characteristics of some types of ceramic capacitors, care
must be taken when these capacitors are used at the input
and output. When a ceramic capacitor is used at the input,
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
Additional input voltage filtering to the SV pin (signal
IN
V ) is made possible by adding optional components R
IN
IN
and C as shown in the Functional Diagram. Generally,
IN2
the inherent supply rejection of the LTC3626 makes the
additionofthesecomponentsunnecessary,however,users
with large, asynchronous noise on the input supply may
choose to populate these components. Typical values for
R and C are 5Ω and 0.33µF respectively.
IN
IN2
V input. Atbest, thisringingcancoupletotheoutputand
IN
The selection of C
is determined by the effective series
OUT
be mistaken as loop instability. At worst, a sudden inrush
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
of current through the long wires can potentially cause a
voltage spike at V large enough to damage the part. For
IN
a more detailed discussion, refer to Application Note 88.
the load transient response. The output ripple, ∆V , is
When choosing the input and output ceramic capacitors
choose the X5R or X7R dielectric formulations. These
dielectrics provide the best temperature and voltage
characteristics for a given value and size.
OUT
approximated by:
1
∆VOUT < ∆IL ESR+
8• f •COUT
INTV Regulator
CC
When using low ESR ceramic capacitors, it is more useful
tochoosetheoutputcapacitorvaluetofulfillachargestor-
age requirement. During a load step, the output capacitor
mustinstantaneouslysupplythecurrenttosupporttheload
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
looptorespondisdependentonthecompensationandthe
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
An internal low dropout (LDO) regulator produces a
3.3V supply voltage used to power much of the internal
LTC3626 circuitry including the power MOSFET gate
drivers. The INTV pin connects to the output of this
CC
regulator and should have a minimum 1μF of decoupling
capacitance to ground. The decoupling capacitor should
have low impedance electrical connections to the INTV
CC
and PGND pins to provide the transient currents required
by the LTC3626. The user may connect a maximum load
current of 5mA to this pin but must take into account the
increased power dissipation and die temperature that
the output drop linearly. The output droop, V
, is
DROOP
usually about 3 times the linear drop of the first cycle.
3626f
15
LTC3626
APPLICATIONS INFORMATION
Minimum Off-Time/On-Time Considerations
results.Furthermore,thissupplyisintendedonlytosupply
additional DC load currents as desired and not intended to
regulate large transient or AC behavior as this may impact
LTC3626 operation.
The minimum off-time is the smallest amount of time that
the LTC3626 requires to turn on the bottom power MOS-
FET, trip the current comparator and turn off the power
MOSFET. This time is typically 40ns. For the controlled
on-time current mode control architecture, the minimum
off-time limit imposes a maximum duty cycle of:
Boost Capacitor
The boost capacitor, C , on the Functional Diagram
BST
is used to create a voltage rail above the applied input
DC
= 1 – (f • t
)
MAX
OFF(MIN)
voltage, V . Specifically, the boost capacitor is charged
IN
where f is the switching frequency and t
is the
to a voltage equal to approximately INTV each time the
OFF(MIN)
CC
minimumoff-time.Ifthemaximumdutycycleissurpassed,
due to a dropping input voltage for example, the output
will drop out of regulation. The minimum input voltage to
avoid this dropout condition is:
bottom power MOSFET is turned on. The charge on this
capacitor is then used to supply the required transient
currentduring theremainderoftheswitching cycle. When
the top MOSFET is turned on, the BOOST pin voltage will
be equal to approximately V + 3.3V. For most applica-
IN
VOUT
V
=
tions a 0.1μF ceramic capacitor will provide adequate
performance.
IN(MIN)
1– f • t
(
)
OFF(MIN)
Users should consider reducing the LTC3626 operating
frequency for applications that may violate the minimum
off-time if constant regulation is required.
Output Voltage Programming
The LTC3626 will adjust the output voltage such that V
equals the reference voltage of 0.6V according to:
FB
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 20ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
R1
R2
VOUT = 0.6V 1+
The desired output voltage is set by the appropriate selec-
tionofresistorsR1andR2asshowninFigure2. Choosing
largevaluesforR1andR2willresultinimprovedefficiency
but may lead to undesired noise coupling or phase margin
reduction due to stray capacitance at the FB node. Care
should be taken to route the FB line away from any noise
source, such as the SW or BOOST lines.
DC
= (f • t
)
MIN
ON(MIN)
where t
is the minimum on-time. As the equation
ON(MIN)
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In rare cases in which the LTC3626’s minimum duty
cycle is surpassed, the output voltage will still remain in
regulation, however the switching frequency will be lower
than its programmed value. This is an acceptable result in
many applications, so high switching frequencies may be
used in the design without fear of severe consequences.
AsthesectionsonInductorandCapacitorSelectionshow,
high switching frequencies allow the use of smaller board
components, thus reducing the footprint of the applica-
tion circuit.
To improve the frequency response of the main control
loop a feedforward capacitor, C , may be used as shown
F
in Figure 2.
V
OUT
R1
C
F
FB
LTC3626
SGND
R2
3626 F02
Figure 2. Optional Feedforward Capacitor
3626f
16
LTC3626
APPLICATIONS INFORMATION
Internal/External Loop Compensation
Checking Transient Response
The LTC3626 provides the option to use a fixed internal
loop compensation network to reduce both the required
external component count and design time. The internal
loop compensation network can be selected by connect-
The regulator loop response can be checked by observing
theresponseofthesystemtoaloadstep.Whenconfigured
for external compensation, the availability of the ITH pin
not only allows optimization of the control loop behavior
butalsoprovidesaDC-coupledandAC-filteredclosed-loop
response test point. The DC step, rise time, and settling
behavior at this test point reflect the system’s closed-
loop response. Assuming a predominantly second order
system, the phase margin and/or damping factor can be
estimated by observing the percentage of overshoot seen
at this pin with a high impedance, low capacitance probe.
ing the ITH pin to the INTV pin. To ensure stability, it
CC
is recommended that the internal compensation be used
at operating frequencies of 1MHz or greater. When using
internal compensation, a reasonable starting point for
the minimum amount of output capacitance necessary
for stability can be found as the greater of either 22µF or
C
OUT
defined by the equation:
70e-6
VOUT
The ITH external components shown in Figure 3 will pro-
vide an adequate starting point for most applications. The
seriesR-Cfiltersetsthepole-zeroloopcompensation.The
values can be modified slightly, from approximately 0.5
to 2 times their suggested values, to optimize transient
responseoncethefinalPClayoutisdoneandtheparticular
output capacitor type and value have been determined.
The specific output capacitors must be selected because
theirvarioustypesandvaluesdeterminetheloopfeedback
factor, gain, and phase. An output current pulse of 20%
to 100% of full load current, with a rise time of 1μs to
10μs, will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
COUT
>
Alternatively, the user may choose specific external loop
compensation components to optimize the main control
loop transient response as desired. External loop com-
pensation is chosen by simply connecting the desired
network to the ITH pin.
Suggested compensation component values are shown
in Figure 3. For a 2MHz application, an R-C (R
and
COMP
C
in Figure 3) network of 220pF and 13kΩ provides
COMP
a good starting point. The bandwidth of the loop increases
with decreasing C. If R is increased by the same factor
that C is decreased, the zero frequency will be kept the
same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. A 10pF
When observing the response of V
to a load step, the
OUT
initialoutputvoltagestepmaynotbewithinthebandwidth
of the feedback loop. As a result, the standard second
order overshoot/DC ratio cannot be used to estimate
phase margin. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For
a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Linear Technology Application Note 76. As shown
bypass capacitor (C
in Figure 3) the ITH pin is recom-
BYP
mended to filter out high frequency coupling from stray
board capacitance. In addition, a feedforward capacitor,
C , can be added to improve the high frequency response,
F
as previously shown in Figure 2. Capacitor C provides
F
phase lead by creating a high frequency zero with R1
which improves the phase margin.
ITH
in Figure 2 a feed-forward capacitor, C , may be added
F
R
COMP
acrossfeedbackresistorR1toimprovethehighfrequency
13k
C
LTC3626
BYP
C
COMP
response of the system. Capacitor C provides phase lead
F
220pF
SGND
by creating a high frequency zero with R1.
3626 F03
Figure 3. Compensation Components
3626f
17
LTC3626
APPLICATIONS INFORMATION
average current limit for either average output current or
average input current may be obtained by placing a resis-
In some applications severe transients can be caused by
switchinginloadswithlarge(>10μF)inputcapacitors.The
discharged input capacitors are effectively put in parallel
tor, R , from the monitor pin to SGND according to the
LIM
following equation:
with C , causing a rapid drop in V . No regulator can
OUT
OUT
deliver enough current to prevent this output droop if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rentlimit,short-circuitprotectionandsoft-startfunctions.
1.2V •16000
RLIM
=
ILIM
where I is the programmed current limit.
LIM
When active, the current limit amplifiers form a feedback
loopthatcontrolsthemaximumaveragecurrentproduced
by the LTC3626. Thus, when using the current limit fea-
ture, a compensation capacitor should be placed between
SGND and the monitor pin of interest. This capacitor,
Input/Output Current Monitor and Limit
The LTC3626 senses the average current through the
synchronous switch during the on state and outputs a
scaled replica of this current (which corresponds to the
combined with the R
resistor, is intended to create a
LIM
dominant pole for compensation purposes. For most ap-
plications, a capacitor with a minimum value of 1µF will
provide adequate loop stability. However, given the wide
variation in loop parameters that depend on specific ap-
plication requirements, loop stability should be confirmed
by stepping the load current to a level that triggers the
programmedcurrentlimit.Theresultanttransientresponse
should provide a sense of the overall loop stability with-
out breaking the feedback loop. The transient response
that results from releasing the current limit should also
be checked. If the transient response waveforms exhibit
excessive ringing, indicating inadequate loop stability,
increase the compensation capacitor value until adequate
stability has been achieved.
regulator’s load current) to the IMON
pin. A mirrored
OUT
version of this signal is modulated with the buck regula-
tor’s duty cycle to provide a scaled replica of the buck
regulator’s input current to the IMON pin. The average
IN
current at each of the monitor pins is 1/16000th the
measured average current. The output current at either
pin may be measured directly or converted to a voltage
with an external resistor.
The average input and output current monitor circuits
both use a chopping technique to achieve high accuracy.
As a result, a small periodic ripple may be seen at either
of these outputs, the average of which is the measured
valueofinterest. Theripplefrequencywillbetheoperating
frequency divided by 256. In addition, the average input
current is measured by modulating the duty cycle of the
average output current leading to an additional ripple at
the operating frequency. If required, a capacitor may be
placed on either output pin to reduce the magnitude of
the ripple.
The simple dominant pole compensation scheme dis-
cussed previously is intended to provide loop stability by
limiting the bandwidth of the current limit feedback loop.
As a result, the average current may momentarily exceed
the programmed limit until the current limit feedback loop
canrespond.Moreadvancedcompensationnetworksmay
be used to potentially reduce the loop response time but
generally require more caution and design expertise. For
example, one technique is to add a low value resistor in
The voltages at the IMON
and IMON pins are con-
IN
OUT
tinuously fed to independent current limit amplifiers that
haveavoltagereferenceof1.2V(typical).Aprogrammable
3626f
18
LTC3626
APPLICATIONS INFORMATION
series with the compensation capacitor. The resistor in
series with the capacitor creates a zero in the current limit
loop transfer function given by:
degrees Celsius, subtract 273 from the value obtained in
degrees Kelvin.
The temperature monitor function uses a chopping tech-
niquetoachievehighprecision.Asaresult,asmallperiodic
ripple may be seen at the TMON pin, the average of which
is the measured value of interest. The ripple frequency will
be the operating frequency divided by 32. If required, a
1µF or greater capacitor to SGND may be placed on the
output to reduce the magnitude of the ripple.
1
fZ =
2•π •RZ •C
whileminimallyimpactingthefrequencyofthecompensa-
tion pole. Given the current limit loop frequency response
containsseveralmoderatefrequencypoles:oneatapproxi-
mately 10kHz (typical) and two at approximately 100kHz
(typical), the placement of the zero in frequency can be
used to provide additional phase margin, which in turn,
may allow a higher loop bandwidth without sacrificing
The temperature monitor output is driven from a flexible,
internallycompensatedon-chipbuffercapableofsourcing
or sinking small amounts of continuous currents (<20µA
typical). The buffer internal compensation is intended
for capacitive loads up to approximately 150pF (typical).
This configuration allows direct connection of TMON to
convenient test equipment, such as a multimeter, for
temperature measurement. The internal compensation
may be overridden by connecting a capacitor of value 1µF
or greater between TMON and SGND. This configuration
allows for a wide range of applications requiring stability
with higher load capacitance, such as some ADC inputs.
loop stability. For example, choosing C = 0.33µF and R =
Z
50 creates a zero at approximately 10kHz thereby reduc-
ing the impact of the internal pole located at that same
frequency. With this compensation scheme, the LTC3626
currentlimitloopwillhaveadominantpolefrequency, and
overall loop bandwidth, roughly three times higher than
that provided with a 1µF capacitor, while likely providing
adequate loop stability.
As previously described, the LTC3626 senses the average
output current through the synchronous FET during the
off time. As a result, it is recommended the LTC3626 be
operated with an off time of greater than 150ns for best
current monitor accuracy. For many applications, this
is of little concern unless operating at or near regulator
dropout conditions (extremely high duty-cycle operation)
and high switching frequencies. Overall, best current
monitor accuracy is achieved with output currents above
approximately 200mA in forced continuous mode with
switching frequencies of 1MHz or lower.
The voltage produced at TMON is continuously fed to
a limit comparator that has the voltage at the TSET pin
as its reference input. When triggered, this comparator
generates an overtemperature fault that will initiate part
shutdown and reset of soft-start. Thus, a programmable
temperature limit may be obtained by providing a voltage
at the TSET pin that corresponds to the temperature limit
of interest. The voltage at the TSET pin may be derived
from a resistor divider from INTV , subject to the current
CC
constraints listed in the Electrical Characteristics section,
or may be driven externally. The LTC3626 will clear the
overtemperature fault and attempt to restart once the in-
ternal temperature falls 10°C (typical) from the threshold
given at TSET. As an example, to set a temperature limit
at approximately 125°C, the voltage at TSET should be:
On-Die Temperature Monitor and Limit
The LTC3626 produces a voltage at the TMON pin propor-
tional to the measured junction temperature. The junction
temperature-to-voltage scaling factor is 200°K/V. Thus,
to obtain the junction temperature in degrees Kelvin,
simply multiply the voltage provided at the TMON pin by
the scaling factor. To obtain the junction temperature in
125°C+ 273
200°K/V
VTSET
=
≈ 2V
3626f
19
LTC3626
APPLICATIONS INFORMATION
MODE/SYNC Operation
above. During normal operation, if the output drops below
10% of its final value, as it may when tracking down for
instance, the regulator will automatically switch to Burst
Modeoperationtopreventinductorsaturationandimprove
TRACK/SS pin accuracy.
The MODE/SYNC pin is a multipurpose pin allowing both
mode selection and operating frequency synchronization.
ConnectingthispintoINTV enablesBurstModeoperation
CC
for superior efficiency at low load currents at the expense
of slightly higher output voltage ripple. When the MODE/
SYNC pin is pulled to ground, forced continuous mode
operation is selected creating the lowest output voltage
ripple at the expense of light load efficiency.
Output Power Good
The PGOOD output of the LTC3626 is driven by a 20Ω
(typical)open-drainpull-downdevice.Thispinwillbecome
high impedance once the output voltage is within 5%
(typical) of the target regulation point allowing the volt-
age at PGOOD to rise via an external pull-up resistor. If
the output voltage exits a 8% (typical) regulation window
around the target regulation point, the open-drain output
will pull down to ground, thereby dropping the PGOOD
pin voltage. A filter time of 40μs (typical) acts to prevent
The LTC3626 will detect the presence of an external clock
signalontheMODE/SYNCpinandsynchronizetheinternal
oscillatortothephaseandfrequencyoftheincomingclock.
The presence of an external clock will place the LTC3626
into forced continuous mode operation.
Output Voltage Tracking and Soft-Start
unwanted PGOOD output changes during V
transient
OUT
The LTC3626 allows the user to control the output volt-
age ramp rate by means of the TRACK/SS pin. From 0V
to 0.6V the TRACK/SS pin will override the internal refer-
ence input to the error amplifier forcing regulation of the
feedback voltage to that seen at the TRACK/SS pin. When
thevoltageattheTRACK/SSpinrisesabove0.6V, tracking
is disabled and the feedback voltage will be regulated to
the internal reference voltage.
events. As a result, the output voltage must be within
the target regulation window of 5% for 40μs before the
PGOOD pin is pulled high. Conversely, the output voltage
must exit the 8% regulation window for 40μs before the
PGOOD pin pulls to ground (see Figure 4).
NOMINAL OUTPUT
The voltage at the TRACK/SS pin may be driven from an
externalsource, oralternatively, theusermayleveragethe
internal 1.4µA (typical) pull-up current on TRACK/SS to
implement a soft-start function by connecting a capacitor
fromtheTRACK/SSpintoground.Therelationshipbetween
output rise time and TRACK/SS capacitance is given by:
PGOOD
VOLTAGE
V
OUT
3626 F04
–8% –5% 0% 5%
8%
Figure 4. PGOOD Pin Behavior
t
= 430,000 • C
TRACK/SS
SS
Efficiency Considerations
A default internal soft-start timer forces a minimum soft-
start time of 400µs (typical) by overriding the TRACK/
SS pin input during this time period. Hence, capacitance
valueslessthanapproximately1000pFwillnotsignificantly
affect soft-start behavior.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
When using the TRACK/SS pin, the regulator defaults to
Burst Mode operation until the output exceeds 80% of
% Efficiency = 100% – (L1 + L2 + L3 +…)
its final value (V > 0.48V). Once the output reaches this
FB
where L1, L2, etc. are the individual loss terms as a per-
centage of input power.
voltage, the operating mode of the regulator switches to
the mode selected by the MODE/SYNC pin as described
3626f
20
LTC3626
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
Other losses, including diode conduction losses during
dead time and inductor core losses, generally account for
less than 2% total additional loss.
losses, three main sources account for the majority of the
2
losses in the LTC3626: 1) I R loss, 2) switching losses
and quiescent current loss, 3) transition losses and other
system losses.
Thermal Considerations
2
The LTC3626 requires the exposed package backplane
metal(PGND)tobewellsolderedtothePCboardtoprovide
good thermal contact. This gives the QFN package excep-
tional thermal properties, compared to other packages
of similar size, making it difficult in normal operation to
exceed the maximum junction temperature of the part. In
many applications, the LTC3626 does not generate much
heat due to its high efficiency and low thermal resistance
package backplane. However, in applications in which
the LTC3626 is running at a high ambient temperature,
high input voltage, high switching frequency, and maxi-
mum output current, the generated heat may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 175°C, both power
switches will be turned off until temperature decreases
approximately 10°C.
1. I R loss is calculated from the DC resistance of the
internal switches, R , and external inductor, R .
SW
L
In continuous mode, the average output current will
flow through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both the top and bottom MOSFET’s R
duty cycle (DC) as follows:
and the
DS(ON)
R
SW
= (R
)(DC) +(R )(1 – DC)
DS(ON)BOT
DS(ON)TOP
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
obtained from the Typical Performance Characteristics
2
curves. Thus to obtain I R loss:
2
2
“I R Loss” = I
• (R + R )
SW L
OUT
2. The internal LDO supplies the power to the INTV rail.
CC
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Thermal analysis should always be performed by the user
to ensure the LTC3626 does not exceed the maximum
junction temperature.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge, dQ, moves
The temperature rise is given by:
from SV to ground. The resulting dQ/dt is a current
T
= P • θ
RISE D JA
IN
out of INTV that is typically much larger than the DC
CC
where P is the power dissipated by the regulator and θ
D
JA
control bias current. In continuous mode, I
=
GATECHG
is the thermal resistance from the junction of the die to
f(Q + Q ), where Q and Q are the gate charges of the
T
B
T
B
the ambient temperature.
internal top and bottom power MOSFETs and f is the
ConsidertheexampleinwhichanLTC3626EUDCisoperat-
switching frequency. For estimation purposes, (Q +
T
ing with I
= 2.5A, PV = SV = 12V, f = 2MHz, V
Q )ontheLTC3626isapproximately2.5nC.To calculate
OUT
IN IN OUT
B
= 1.8V, and an ambient temperature of 70°C. From the
the total power loss from the LDO load, simply add the
Typical Performance Characteristics section the R
gate charge current and quiescent current and multiply
DS(ON)
of the top switch is found to be nominally 130mΩ while
by SV :
IN
that of the bottom switch is nominally 85mΩ yielding an
P
= (I + I ) • V
GATECHG Q IN
LDO
equivalent power MOSFET resistance R of:
SW
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends in
the saturated region during switch node transitions.
1.8
12
10.2
12
RDS(ON)TOP
•
+ RDS(ON)BOT
•
= 92mW
3626f
21
LTC3626
APPLICATIONS INFORMATION
4. Keep sensitive components away from the SW and
Fromtheprevioussection,I
isapproximately5mA
GATECHG
BOOST pins. The R resistor, the feedback resistors,
when f = 2MHz, and the spec table lists the typical I to be
RT
Q
the compensation components, the current monitor
approximately1mA.Therefore,thetotalpowerdissipation
due to resistive losses and LDO losses is:
components, and the INTV bypass capacitor should
CC
all be routed away from the SW trace and the inductor.
2
P = I
D
• R + V • (I
+ I )
GATECHG Q
OUT
SW
IN
5. A ground plane is preferred, but if not available the
signal and power grounds should be segregated with
both connecting to a common, low noise reference
point. The point at which the ground terminals of the
2
P = (2.5A) • (0.092Ω) + 12V • 5mA = 635mW
D
TheQFN3mm× 4mmpackagejunction-to-ambientthermal
resistance, θ , is approximately 47°C/W. Therefore, the
JA
junction temperature of the regulator operating in a 70°C
V and V
IN
bypass capacitors are connected makes a
OUT
ambient temperature is approximately:
good, low noise reference point. The connection to the
PGND pin should be made with a minimal resistance
trace from the reference point.
T = 0.63W • 47°C/W + 70°C = 100°C
J
which is below the maximum junction temperature of
125°C.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
Thesecopperareasshouldbeconnectedtotheexposed
backside connection of the IC.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3626.
Design Example
As a design example, consider using the LTC3626 in an
application with the following specifications:
1. Does the capacitor C connect to PV and PGND as
IN
IN
close to the pins as possible? These capacitors provide
V
IN
= 12V, V
= 1.8V, I
= 2.5A, I
=
OUT
OUT(MAX)
OUT(MIN)
the AC current to the internal power MOSFETs. The (–)
50mA
Further, the ability to continuously monitor the average
output current (I ) and the internal temperature is de-
plate of C should be closely connected to PGND and
IN
the (–) plate of C
.
OUT
OUT
2. The output capacitor, C , and inductor L1 should
OUT
sired. Finally, an average I
temperature limit of approximately 125°C are desired.
limit of 2.5A and an internal
OUT
be closely connected to minimize loss. The (–) plate
of C
should be closely connected to PGND and the
OUT
(–) plate of C .
Because efficiency is important at both high and low load
currents, Burst Mode operation and 1MHz operation is
chosen.
IN
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
and a ground line termi-
OUT
nated near SGND. The feedback signal, V , should be
First, the correct R resistor value for 1MHz switching
FB
RT
routedawayfromnoisycomponentsandtracessuchas
the SW and BOOST lines, and its trace length should be
minimized.Inaddition,RT,compensationcomponents,
andcurrentandtemperaturemonitor/limitcomponents
should be terminated to SGND.
frequency must be chosen. Based on the equation in the
Applications Information section, R is calculated to be
RT
320k. A standard 324k resistor is selected for R .
RT
3626f
22
LTC3626
APPLICATIONS INFORMATION
Next, determine the inductor value for approximately 40%
ripple current using:
To save board space, the ITH pin is connected to INTV
to select the internal compensation network.
CC
The PGOOD pin is connected to V through a 100k resis-
1.8V
1MHz •1A
1.8V
12V
IN
L =
1–
= 1.53µH
tor to INTV .
CC
To program the I
limit at 2.5A, a resistor is connected
OUT
Astandard1.5µHinductorwillworkwellforthisapplication.
Next, C is selected based on the required output tran-
sient performance and the required ESR to satisfy the
output voltage ripple. For this design, two 22µF ceramic
capacitors will be used.
betweenIMON
andSGNDwithadesiredvalueequalto:
OUT
OUT
16,000•1.2V
RIOUT
=
= 7.68kW
2.5A
Thus, a standard 7.68kΩ will be selected for R
capacitor placed in parallel with R
compensation should be adequate for most applications.
. A 1µF
IOUT
for I
limit loop
IOUT
OUT
C should be sized for a maximum current rating of:
IN
1.8V 12V –1.8V
(
)
The 125°C temperature limit is programmed by setting a
voltage at the TSET pin equal to:
IRMS = 2.5A •
= 0.89A
12V
Decoupling the PV pin with a 47µF ceramic capacitor
IN
125°C+ 273
200°K/V
VTSET
=
≈ 2V
should be adequate for most applications. An additional
1µF capacitor on the PV can be used to help reduce
IN
ringing as required. A 0.33µF capacitor on the SV pin is
In this example, the TSET voltage will be derived by divid-
IN
optional and will be tied to PV through a 5Ω resistor for
ing the available INTV voltage using R = 432k and
IN
CC
TSET1
additional filtering at the SV pin. Finally, a 0.1µF boost
R
= 665k.
TSET2
IN
capacitor should work for most applications.
V
IN
PV
SV
IN
IN
12V
C
C
IN2
1µF
IN1
BOOST
LTC3626
47µF
C3
0.33µF
C
R3
5Ω
RUN
BST
0.1µF
L1
1.5µH
INTV
V
1.8V
2.5A
CC
OUT
C
INTVCC
TRACK/SS
ITH
SW
R
2.2µF
R
TSET1
432k
PGD
C
C
OUT
47µF
F
100k
R1
40.2k
22pF
MODE/SYNC
V
ON
IMON
IN
PGOOD
TMON
TSET
FB
R2
20k
RT
IMON
OUT
R
3626 F07
TSET2
R
T
SGND
PGND
C
665k
R
IOUT
IOUT
324k
1µF
7.68k
Figure 7. 12V Input to 1.8V Output, 2.5A Regulator at 1MHz in Burst Mode Operation with
Output Current Monitor and 2.5A Limit, On-Die Temperature Monitor and 125°C Limit
3626f
23
LTC3626
TYPICAL APPLICATIONS
12V Input to 5V Output at 2MHz
V
IN
PV
SV
IN
IN
12V
C1
47µF
BOOST
C
BSTA
C3A
0.33µF
R3A
5Ω
RUN
0.1µF
LTC3626
PGOOD
L1A
1.5µH
INTV
RT
V
CC
OUT
SW
5V
TSET
C
C
2.5A
FA
OUTA
R1A
TMON
IMON
IMON
22pF
47µF
V
ON
294k
IN
OUT
C4A
2.2µF
FB
R2A
40.2k
TRACK/SS
ITH
SGND
MODE/SYNC
PGND
R
COMPA
13k
C
COMPA
220pF
PV
SV
IN
IN
BOOST
SW
C
BSTB
C3B
R3B
5Ω
RUN
0.1µF
0.33µF
LTC3626
PGOOD
INTV
RT
TSET
TMON
IMON
IMON
TRACK/SS
L1B
1.5µH
CC
C4B
2.2µF
C
C
OUTB
47µF
FB
R1B
294k
22pF
V
ON
IN
OUT
FB
R2B
40.2k
ITH
SGND
MODE/SYNC
PGND
R
COMPB
13k
C
COMPB
V
220pF
OUT
–5V
1.2A
3626f
24
LTC3626
TYPICAL APPLICATIONS
5V Input to 2.5V Output at 1MHz Synchronized Frequency with
Input Current Monitor and 475mA Input Current Limit
V
IN
PV
SV
IN
IN
5V
C1
47µF
BOOST
C
RUN
BST
0.1µF
L1
2.2µH
LTC3626
TRACK/SS
V
2.5V
2.5A
OUT
INTV
RT
CC
C4
2.2µF
C
C
OUT
47µF
SW
F
R
R1
127k
PGD
22pF
TSET
100k
IMON
V
ON
OUT
TMON
PGOOD
ITH
R2
FB
40.2k
R
13k
C
IMON MODE/SYNC
COMP
IN
3626 TA03
R
C
IIN
IIN
EXTERNAL
CLOCK
40.2k
1µF
SGND
PGND
COMP
220pF
3626f
25
LTC3626
TYPICAL APPLICATIONS
12V Input to 5V Output and 500mA Charger for Battery Backup System
V
IN
PV
SV
IN
IN
12V TO 20V
C
IN1
47µF
BOOST
C
BST1
RUN
0.1µF
LTC3626
CC
TRACK/SS
TMON
TSET
L1
1µH
INTV
5V
C
VCC1
2.2µF
SW
R
0Ω
C
F1
22pF
C
ON
OUT1
47µF
4.2V
R
V
ON
FB1
110k
RT
ITH
FB
MODE/SYNC
R
FB3
15k
I
I
D1
GRN
D3
D2
D4
RED
IN
OUT
RED GRN
R
PG1
100k
R1
R3
1k
R2
1k
R4
1k
PGOOD
SGND
1k
PGND
LTC4415
14
13
12
11
IN1
EN1
STAT1
WARN1
D5
PV
IN
SV
IN
CLIM1 WARN2
CLIM2 STAT2
C
IN2
BOOST
47µF
C
BST2
3626 TA05
R
R
D2
1k
SYSTEM
LOAD
D1
LTC3626
0.1µF
OUT1
200Ω
C
OUT3
CHARGE CONTROL
RUN
L2
EN2
10µF
1µH
V
ON
C
VCC2
INTVCC
TRACK/SS
TMON
SW
FB
IN2
OUT2
GND
+
2.2µF
C
10µF
Li-Ion
BATTERY
4.2V
OUT4
C
OUT2
47µF
C
F2
R
FB2
1.15M
220pF
TSET
RT
ITH
R
FB4
191k
MODE/SYNC
I
I
IN
OUT
R
C
R
100k
IOUT
PG2
IOUT
1µF
38.3k
PGOOD
SGND
PGND
3626f
26
LTC3626
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
2.65 ± 0.05
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ± 0.05
× 45° CHAMFER
1.50 REF
19 20
R = 0.05 TYP
3.00 ± 0.10
0.40 ± 0.10
1
2
PIN 1
TOP MARK
(NOTE 6)
2.65 ± 0.10
1.65 ± 0.10
4.00 ± 0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3626f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3626
TYPICAL APPLICATION
12V Input to 1.8V Output, 2.5A Regulator with Digital Output Current Monitoring
V
IN
PV
SV
IN
IN
12V
C1
47µF
C2
1µF
BOOST
C
BST
RUN
LTC3626
0.1µF
L1
1.5µH
INTV
ITH
TRACK/SS
TSET
TMON
IMON
PGOOD
IMON
V
1.8V
2.5A
0.1µF
CC
OUT
C4
SW
2.2µF
C
C
OUT
47µF
R
F
PGD
0.1µF
R1
V
ON
22pF
200k
40.2k
0.1µF
FB
RT
IN
REFOUT COMP
V
CC
R2
20k
IN
MODE/SYNC
R
T
324k
OUT
SCK
SDO
CS
R
IOUT
C
1µF
IOUT
3626 TA04
LTC2460
SGND
PGND
5.1k
–
GND
REF
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
95% Efficiency, V : 4.5V to 15V, V
LTC3601
LTC3603
LTC3633
LTC3605A
LTC3604
15V, 1.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
= 0.6V, I = 300µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
I
< 1µA, 4mm × 4mm QFN-20, MSOP-16E
SD
15V, 2.5A (I ), 3MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 4.5V to 15V, V
= 0.6V, I = 75µA,
Q
OUT
IN
I
< 1µA, 4mm × 4mm QFN-20, MSOP-16E
SD
15V, Dual 3A (I ), 4MHz, Synchronous Step-Down DC/DC
95% Efficiency, V : 3.6V to 15V, V
= 0.6V, I = 500µA,
OUT
IN
OUT(MIN) Q
Converter
I
< 15µA, 4mm × 5mm QFN-28, MSOP-28E
SD
20V, 5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 4V to 20V, V
SD
= 0.6V, I = 2mA,
OUT
IN
OUT(MIN) Q
I
< 15µA, 4mm × 4mm QFN-24
15V, 2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 3.6V to 15V, V
SD
= 0.6V, I = 300µA,
OUT
IN
OUT(MIN) Q
I
< 15µA, 3mm × 3mm QFN-16, MSOP-16E
3626f
LT 0712 • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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